[DTrace-devel] [PATCH v2] cg: fix masking of lower 32 bits
Kris Van Hees
kris.van.hees at oracle.com
Wed Sep 24 01:48:21 UTC 2025
The "and %r0, 0xffffffff' instruction does not actually mask off the
lower 32 bits as one would expect because 0xffffffff is interpreted as
-1 and then sign-extended to a 64-bit value, i.e. keeping all bits.
The "mov32 %r0, %r0" instruction does correctly mask off the lower 32
bits because it forced the value in %r0 to be a 32-bit value.
Signed-off-by: Kris Van Hees <kris.van.hees at oracle.com>
---
include/bpf_asm.h | 11 +++++++++++
libdtrace/dt_cg.c | 3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/bpf_asm.h b/include/bpf_asm.h
index 152d2312..63987e01 100644
--- a/include/bpf_asm.h
+++ b/include/bpf_asm.h
@@ -36,6 +36,15 @@
.imm = 0 \
})
+#define BPF_ALU32_REG(op, dst, src) \
+ ((struct bpf_insn) { \
+ .code = BPF_ALU | (op) | BPF_X, \
+ .dst_reg = (dst), \
+ .src_reg = (src), \
+ .off = 0, \
+ .imm = 0 \
+ })
+
#define BPF_END_REG(sz, dst, dir) \
((struct bpf_insn) { \
.code = BPF_ALU | BPF_END | (dir), \
@@ -68,6 +77,8 @@
#define BPF_MOV_REG(dst, src) BPF_ALU64_REG(BPF_MOV, dst, src)
#define BPF_MOV_IMM(dst, val) BPF_ALU64_IMM(BPF_MOV, dst, val)
+#define BPF_MOV32_REG(dst, src) BPF_ALU32_REG(BPF_MOV, dst, src)
+
#define BPF_LOAD(sz, dst, src, ofs) \
((struct bpf_insn) { \
.code = BPF_LDX | BPF_MEM | (sz), \
diff --git a/libdtrace/dt_cg.c b/libdtrace/dt_cg.c
index a8f2c9d2..28b7e7c4 100644
--- a/libdtrace/dt_cg.c
+++ b/libdtrace/dt_cg.c
@@ -2757,7 +2757,8 @@ dt_cg_act_stack_sub(dt_pcb_t *pcb, dt_node_t *dnp, int reg, int off, dtrace_actk
dt_regset_xalloc(drp, BPF_REG_0);
emit(dlp, BPF_CALL_HELPER(BPF_FUNC_get_current_pid_tgid));
dt_regset_free_args(drp);
- emit(dlp, BPF_ALU64_IMM(BPF_AND, BPF_REG_0, 0xffffffff));
+ /* mov32 %r0, %r0 effectively masks the lower 32 bits. */
+ emit(dlp, BPF_MOV32_REG(BPF_REG_0, BPF_REG_0));
emit(dlp, BPF_STORE(BPF_DW, reg, off, BPF_REG_0));
dt_regset_free(drp, BPF_REG_0);
}
--
2.43.5
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